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Sudeep Bhoja

Co-founder and CTO, d-Matrix

Sudeep Bhoja is a co-founder and the Chief Technology Officer of d-Matrix, which builds memory-centric hardware for AI inference. Bhoja has written about the company's 3D stacked digital in-memory compute (3DIMC) roadmap and previewed its 3D DRAM technology at the 2026 Hot Chips conference.123

At a glance

Current role
Co-founder and CTO
Company
d-Matrix
Sector
Company
Work listed
2
Sources cited
4
Profile reviewed

Research and technology

In an August 2025 post, Bhoja argued that the growing cost of AI inference stems from memory, not just compute, and described d-Matrix's early decision to focus on transformer inference with a chiplet-based Corsair accelerator. The post announced 3DIMC on the roadmap and said the first 3DIMC silicon, Pavehawk, was operating in the lab.2

At Hot Chips 2026, Bhoja previewed the 3D DRAM approach used in Raptor, which joins a DRAM memory chip and an SRAM compute chip into a single stacked unit.3

Products and projects

d-Matrix builds memory-centric hardware for AI inference. Its Corsair accelerator uses a chiplet-based digital in-memory compute design, and in August 2025 the company added 3D stacked digital in-memory compute (3DIMC) to its roadmap with Pavehawk, its first 3DIMC silicon.2

In September 2026 d-Matrix announced a collaboration with NVIDIA built around an NVLink Fusion rack-level system and introduced Raptor, a follow-on platform that stacks DRAM on an SRAM compute chip. In October 2026 it announced Squadron, a fleet of multi-rack inference systems, and said its Corsair servers and SquadRacks were generally available.34

Work and contributions

  • 3DIMC and Pavehawk

    Author of the August 2025 post announcing 3D stacked digital in-memory compute on d-Matrix's roadmap, with Pavehawk as its first 3DIMC silicon, aimed at the memory limits of AI inference.2

  • Raptor 3D DRAM platform

    Previewed the 3D DRAM stacking technology behind d-Matrix's Raptor platform at Hot Chips 2026; technical details were also published by IEEE.3

Timeline

  1. d-Matrix added 3D stacked digital in-memory compute to its roadmap with Pavehawk silicon.2
  2. d-Matrix announced a collaboration with NVIDIA on NVLink Fusion rack-scale inference.3
  3. d-Matrix unveiled Squadron multi-rack inference systems at the OCP Global Summit.4

Where they work

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References

4 sources · profile reviewed Oct 21, 2026 · data updated Oct 21, 2026

  1. About d-Matrix — leadershipd-Matrix · Official page · accessed Oct 21, 2026 · reviewed Oct 21, 2026
  2. Scaling AI inference with 3DIMC (d-Matrix blog, by Sudeep Bhoja)d-Matrix · Announcement · published Aug 25, 2025 · accessed Oct 21, 2026 · reviewed Oct 21, 2026
  3. d-Matrix announces collaboration with NVIDIA on NVLink Fusion rack-scale inferenced-Matrix · Announcement · published Sep 10, 2026 · accessed Oct 21, 2026 · reviewed Oct 21, 2026
  4. d-Matrix announces Squadron multi-rack inference compute clustersd-Matrix · Announcement · published Oct 12, 2026 · accessed Oct 21, 2026 · reviewed Oct 21, 2026