David Patterson

Career

David Patterson joined the University of California, Berkeley in 1976 after completing a PhD in computer science at UCLA, and spent four decades there before working at Google for a decade. At Berkeley, Patterson chaired the Computer Science Division; Patterson also chaired the Computing Research Association and served as President of ACM.²¹

Patterson is now the Pardee Professor of Computer Science, Emeritus, at Berkeley, a Google Fellow, and Board Chair of the Laude Institute. Berkeley's faculty page describes Patterson's research style as gathering interdisciplinary groups of faculty and students around a question for the computing industry and answering it with demonstration systems.¹²

Research

Patterson's Berkeley projects included Reduced Instruction Set Computers (RISC), Redundant Array of Inexpensive Disks (RAID), and Networks of Workstations (NOW). Berkeley lists computer architecture, performance, security, and RISC-V among Patterson's research areas.²

At Google, Patterson co-authored the 2017 analysis of the Tensor Processing Unit, a custom chip for neural network inference in Google datacenters, and later papers on TPU v4i, TPU v4, and five generations of Google's training supercomputers through Ironwood. Patterson was also a co-author of the MLPerf Training Benchmark paper and of papers on the carbon footprint and energy use of machine learning.³²¹⁴

Teaching and writing

Patterson has co-authored seven books, including two with John Hennessy. Among them are Computer Architecture: A Quantitative Approach, now in its 7th edition, Computer Organization and Design in a RISC-V edition, and The RISC-V Reader with Andrew Waterman.¹²

Work and contributions

• MLPerf Training Benchmark Published research

  Co-author of the MLPerf Training Benchmark paper (arXiv 2019; MLSys 2020), which Berkeley's faculty page lists among Patterson's selected publications.⁴²

• Tensor Processing Unit (TPU) papers Published research

  Co-author of In-Datacenter Performance Analysis of a Tensor Processing Unit (2017), which evaluates a custom ASIC deployed in Google datacenters since 2015 for neural network inference, and of later papers on TPU v4 and Google's training supercomputers.³²¹

• Computer Architecture: A Quantitative Approach

  Co-author, with John Hennessy, of a computer architecture textbook whose 7th edition (2026, with Christos Kozyrakis) is listed first among Patterson's selected publications at Berkeley.²¹

Timeline

1. 1976Completed a PhD in computer science at UCLA and joined UC Berkeley.²
2. 2017Published The RISC-V Reader with Andrew Waterman.²
3. Apr 16, 2017Co-authored In-Datacenter Performance Analysis of a Tensor Processing Unit.³
4. Oct 2, 2019Co-authored the MLPerf Training Benchmark paper, later presented at MLSys 2020.⁴²
5. 2023Co-authored the ISCA 2023 paper on TPU v4, an optically reconfigurable supercomputer for machine learning.²
6. 2026Published the 7th edition of Computer Architecture with John Hennessy and Christos Kozyrakis.²

Honors and recognition

• ACM A.M. Turing Award · Association for Computing Machinery, 2017¹
• Charles Stark Draper Prize for Engineering · National Academy of Engineering, 2022¹
• IEEE John von Neumann Medal · IEEE²
• ACM-IEEE Eckert-Mauchly Award · ACM and IEEE Computer Society²
• Member, National Academy of Engineering · National Academy of Engineering²
• Member, National Academy of Sciences · National Academy of Sciences²

Where they work

• Google 121 people in the wiki
• UC Berkeley 27 people in the wiki
• Laude Institute 1 person in the wiki

Related people

• Cho-Jui HsiehAlso at Google
• Adam PaszkeAlso at Google
• Jeff DeanAlso at Google
• Margaret MitchellAlso at Google
• James BradburyAlso at Google
• Chase LochmillerChips and hardware · Training systems
• Naveen RaoChips and hardware · Training systems
• Michael CarbinTraining systems · Chips and hardware
• Cully CavnessChips and hardware · Training systems
• Akshita BhagiaEvaluation and benchmarks · Training systems