Andrew Waterman is a co-founder and the Chief Engineer of SiFive, the RISC-V processor IP company. SiFive credits its founders, Waterman, Krste Asanović and Yunsup Lee, working with David Patterson, with creating RISC-V at UC Berkeley starting in 2010. Waterman is first author of the 2011 RISC-V Instruction Set Manual technical report and wrote the 2016 Berkeley dissertation "Design of the RISC-V Instruction Set Architecture".1234
At a glance
- Current role
- Co-founder and Chief Engineer
- Company
- SiFive
- Sector
- Company
- Fields
- Chips and hardware
- Education
- UC Berkeley
- Work listed
- 3
- Sources cited
- 6
- Profile reviewed
Research
Waterman's doctoral work at UC Berkeley, advised by David A. Patterson and Krste Asanović, centered on the instruction set architecture as the hardware-software interface. The 2016 dissertation argues that a free and open ISA standard could increase innovation in microprocessor design, lower system costs and ease the move to more specialized computing devices.4
Waterman is first author of the 2011 report "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA", written with Yunsup Lee, Patterson and Asanović. Waterman is also a co-author of the 2016 Rocket Chip Generator report, which describes Berkeley's generator for RISC-V processor systems.35
SiFive
SiFive was founded in 2015 by the creators of RISC-V, and its leadership page lists Waterman as Co-Founder and Chief Engineer alongside Asanović as Chief Architect and Lee as Chief Technology Officer. SiFive develops RISC-V processor core IP, with product lines that include its Essential, Intelligence and Performance families.21
Work and contributions
RISC-V Instruction Set Manual, Volume I Published research
First author, with Yunsup Lee, David A. Patterson and Krste Asanović, of the 2011 Berkeley technical report specifying the RISC-V base user-level ISA.3
Design of the RISC-V Instruction Set Architecture Published research
Waterman's 2016 dissertation, which argues for a free and open ISA standard and documents the design of RISC-V.4
Rocket Chip Generator Open-source code
Co-author of the 2016 Berkeley technical report describing the Rocket Chip generator for RISC-V systems-on-chip, now maintained as an open-source repository under CHIPS Alliance.56
Timeline
- Began work on RISC-V as part of a Berkeley summer project with Asanović, Lee and Patterson.2
- First-authored the RISC-V Instruction Set Manual, Volume I technical report.3
- Co-founded SiFive with Krste Asanović and Yunsup Lee.21
- Completed the dissertation "Design of the RISC-V Instruction Set Architecture" at UC Berkeley.4
- Co-authored the Rocket Chip Generator technical report.5
Other documented roles
Roles the sources document that are not confirmed as current.
- PhD research in the EECS Department, advised by David A. Patterson and Krste Asanović (dissertation 2016), University of California, Berkeley4
Where they work
- SiFive 3 people in the wiki
Related people
- Krste AsanovićAlso at SiFive
- Chris LattnerAlso at SiFive
- David KanterChips and hardware
- Robert WachenChips and hardware
- Chuck RobbinsChips and hardware
- Song HanChips and hardware
- Daniel GrossChips and hardware
- Cully CavnessChips and hardware
- Marques BrownleeChips and hardware
- Darío GilChips and hardware
Suggest a correction or removal
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References
6 sources · profile reviewed Oct 21, 2026 · data updated Oct 21, 2026